Research on time reference determination and phase calibration method of high precision measurement system
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摘要: 针对高精度测量系统的时间基准确定和相位校准需求,提出了一种时间基准的高精度相位确定和校准方法,以解决系统中校准精度较低的问题. 该方法利用现场可编程门阵列（FPGA）延迟线对时间基准进行延时控制并且结合相位跳变检测技术.首先准确判断时间基准在被系统时钟采样时发生相位跳变的区间,其次准确测量出稳定时间基准所需要的延时值,最后对时间基准进行内部延迟,并对延迟后的时间基准进行系统同步. 所提方法具有校准精度高、设计简洁的特点. 搭建了一套仿真验证平台并结合计算机对所提方法进行了功能性验证.所提方法已应用在高精度测量系统中.Abstract: Aiming at the requirements of time reference determination and phase calibration of high-precision measurement systems, a high-precision phase determination and calibration method of time reference is proposed to solve the problem of low calibration accuracy in the system. This method uses FPGA delay lines to perform time reference Delay control combined with phase jump detection technology. First, accurately determine the interval where the phase transition occurs when the time reference is sampled by the system clock; second, accurately measure the delay value required to stabilize the time reference, and finally perform the time reference internal delay, and system synchronization of the delayed time reference. The proposed method has the characteristics of high calibration accuracy and low complexity. A simulation verification platform was built and the functional verification of the proposed method was performed in conjunction with a computer. The method has been applied to highprecision measurement systems.
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Key words:
- time reference /
- phase calibration /
- phase jump /
- pulse per second signal
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[1] 伍贻威. 卫星导航系统时间尺度的研究与应用［D］. 长沙：国防科学技术大学,2011. [2] CHEN L, LI C, LI P. Accuracy Analysis of BOC Signal Dual Sideband Algorithm on NonIdeal Channel［C］// China Satellite Navigation Conference (CSNC) 2012 Proceedings, 2012(161): 415-427.DOI: 10.1007／978-3-642-29193-7_40. [3] 拉贝艾. 数字集成电路:电路、系统与设计(第二版)［M］. 周润德, 译. 北京: 电子工业出版社, 2004:237-239. [4] CHEN L, LI J Y, HUANG Y B, et al. System clock and time reference ambiguity solution method based on clock quartering［C］// China Satellite Navigation Conference (CSNC) 2014 Proceedings,2014(303): 703-713. DOI: 10.1007／978-3-642-54737-9_61. [5] 周晖, 宣宗强, 周渭. 基于等效鉴相频率的频标比对途径［J］. 电子科技, 2004(4):25-27,33. [6] ZHOU W, WANG H. Development of the measurement and control technique in time and frequency［J］. Journal of time and frequency, 2003(26): 87-95. DOI: 10.1023／A:1022289509702. [7] 叶林, 周弘, 张洪, 等. 相位差的几种测量方法和测量精度分析［J］. 电测与仪表, 2006,43(4):11-14. [8] 张延. 用FPGA实现高精度时间间隔测量［D］.上海：中国科学院研究生院(上海天文台),2006. [9] 陈昱宇. 新型延迟线的研究［D］.成都：电子科技大学,2009. [10] BEEK D E VAN，R C H，KLUMPERINK E A M，VAUCHER C S，et al. Low-jitter clock multiplication:a comparison between PLLs and DLLs［J］. IEEE transaction on circuits and system II analog and digital signal processing,2002,49(8): 555-566. DOI: 10.1109／TCSII.2002.806248． [11] 胡华春,石玉.数字锁相环路原理与应用［M］.上海:上海科学技术出版社,1990:250-271. [12] CARLEPP B W,DONNELLY K S,KIMJ,et al.A portable digital DLL for high-speed CMOS interface circuits［J］.IEEE journal of solid-state circuits.1999,34 (5):632-644. DOI: 10.1109／4.760373. [13] Xilinx Co. Spartan-IIE 1.8V FPGA family: complete data sheet［M/OL］.［2020-02-16］. http:／／ece-research.unm.edu／pollard／classes／447／SpartanIIE.pdf.［14 ] Xilinx Co. VirtexTM -E 1.8V field programmable gate array［M/OL］.［2020-02-16］ ,https:／／www.xilinx.com／support／documentation／data_sheets／ds022. pdf. [14] Altera Co. Cyclone device handbook, volume l［M/OL］.［2020-02-10］. https:／／www.intel.com／content／dam／www／programmable／us／en／pdfs／literature／hb／cyc／cyc_c5v1.pdf. [15] Altera Co. Stratix device handbook, volume l［M/OL］.［2020-02-11］. https:／／www.intel.com／content／dam／www／programmable／us／en／pdfs／literature／hb／stx／stratix_handbook.pdf. -
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