Abstract: With the application of comb filters in Loran-C Navigation System (Loran-C) receivers, the cross interference of such receivers has been significantly suppressed. However, this algorithm consumes a large amount of block random access memory (BRAM) resources on field programmable gate array (FPGA). The comb filter algorithm for a single chain can occupy 60% to 70% of the BRAM resources of mainstream FPGA chips, which greatly limits its scope and performance in practical engineering applications. Accordingly, this paper proposes an implementation scheme of the comb filter algorithm on FPGA by adopting external double data rate synchronous dynamic random access memory (DDR). DDR features fast read/write speed and large data throughput. It can process Loran-C signals from 4 to 5 chains simultaneously without occupying on-chip FPGA resources. As an optimal solution for implementing the comb filter algorithm, this method possesses high practical engineering value.