GNSS World of China

Volume 45 Issue 1
Feb.  2020
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PAN Weizhuang, WANG Lu, XIA Xiaoyu. A low-power design technique for GNSS anti-jam processor[J]. GNSS World of China, 2020, 45(1): 56-60. doi: DOI:10.13442/j.gnss.1008-9268.2020.01.009
Citation: PAN Weizhuang, WANG Lu, XIA Xiaoyu. A low-power design technique for GNSS anti-jam processor[J]. GNSS World of China, 2020, 45(1): 56-60. doi: DOI:10.13442/j.gnss.1008-9268.2020.01.009
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A low-power design technique for GNSS anti-jam processor

doi: DOI:10.13442/j.gnss.1008-9268.2020.01.009

  • Guangzhou Haige Communication Group Incorporated Company,Guangzhou 510663, China

  • Publish Date: 2020-02-15
    Abstract
  • This paper presents a low-power anti-jamming processor for Global Navigation Satellite System (GNSS) smart antenna. By improving the design of mixer in GNSS anti-interference architecture, the digital high intermediate frequency mixer and filter are optimized. To further reduce the power consumption and resource occupation, an Output Double-Rate-Register(ODDR) scheme is introduced to realize the direct synthesis of high intermediate frequency signal. The experimental results show that the power consumption and hardware resources of this design are reduced by 11％ and 14％, which can be applied to GNSS smart antenna system.

     

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