A method for designing the loop parameters of digital PLL based on equivalent signal model

Ideally, the loop parameters of an digital phase-locked loop (DPLL) is determined by the intersection of the phase noise of the input signal and the voltage-controlled oscillator (VCO). However, the basic module of the phase-locked loop (PLL) will introduce noise into the PLL system, thereby affecting the PLL performance. The method of directly calculating the intersection point of the two cannot take into account the influence of module noise. With the theory of the power-law spectrum model, this paper uses the PLL transfer model to superimpose the noise of the basic module of the PLL on the signal model of the atomic clock and the VCO. After establishing new signal models, it can conveniently and quickly determine the optimal loop parameters of the PLL. The simulation shows that the loop parameters selected by this method can make the output signal have good frequency stability, which can provide theoretical guidance for the selection of the loop parameters of the digital phase-locked device used to purify the atomic clock signal.