A method for designing the loop parameters of digital PLL based on equivalent signal model
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摘要: 理想情况下，数字锁相环(DPLL)的环路参数可以通过直接计算输入原子钟与压控振荡器(VCO)的相位噪声功率谱交点来确定. 但该方法不能考虑到锁相环(PLL)其他模块的噪声，这会导致输出性能恶化. 针对这一问题，文中从PLL模型出发，基于PLL环路传递函数和幂律谱模型，提出PLL模块噪声的等效方法. 该方法将PLL各模块噪声分别等效到输入和VCO的相位噪声上，使得PLL的噪声传递模型只含有等效输入噪声和等效VCO噪声. 然后可以直接计算两者相位噪声交点并设置合理的环路参数. 通过该方法确定的环路参数可以充分结合输入原子钟信号和VCO信号的相位噪声和频率稳定度特性，弥补了直接计算交点法不能考虑模块噪声的缺点. 实验表明：文中方法所选择的环路参数能使得输出信号具备良好的稳定度，可以为应用于净化原子钟信号的数字锁相装置环路参数的确定提供理论指导.Abstract: Ideally, the loop parameters of an digital phase-locked loop (DPLL) is determined by the intersection of the phase noise of the input signal and the voltage-controlled oscillator (VCO). However, the basic module of the phase-locked loop (PLL) will introduce noise into the PLL system, thereby affecting the PLL performance. The method of directly calculating the intersection point of the two cannot take into account the influence of module noise. With the theory of the power-law spectrum model, this paper uses the PLL transfer model to superimpose the noise of the basic module of the PLL on the signal model of the atomic clock and the VCO. After establishing new signal models, it can conveniently and quickly determine the optimal loop parameters of the PLL. The simulation shows that the loop parameters selected by this method can make the output signal have good frequency stability, which can provide theoretical guidance for the selection of the loop parameters of the digital phase-locked device used to purify the atomic clock signal.
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