Design and implementation of closed tracking loop of navigation receiver based on SoC
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摘要: 在传统基于FPGA+DSP架构的导航接收机中，跟踪模块处于开环处理模式，存在实时性和可靠性差的问题，同时现场可编程逻辑门阵列(FPGA)和数字信号处理(DSP)之间大量的数据通信导致了IO资源和功耗的增加. 基于片上系统(SoC)架构提出了一种卫星导航接收机的闭环跟踪环路方案，整个跟踪处理过程在FPGA内实现了完整的闭环处理，有效地解决了开环跟踪存在的问题，极大地减少了FPGA与CPU之间的数据通信量. 此外，所有跟踪通道通过时、分复用的方式共用一个跟踪环路处理模块，有效节约了硬件资源，降低了成本，为小型化、低功耗卫星导航芯片的设计与发展奠定了基础.Abstract: The traditional satellite navigation receiver is based on FPGA+DSP architecture. Under this architecture, the tracking module is in an open-loop processing mode. It has the problems of poor real-time performance and poor reliability. At the same time, a large amount of data communication between FPGA and DSP has led to an increase in IO resources and power consumption. Based on the SoC architecture, a closed-loop tracking loop scheme for satellite navigation receiver is proposed in this paper. The entire tracking process is processed in a closed loop within the FPGA. This effectively solves the problems of open-loop tracking, and greatly reduces the amount of data communication between FPGA and CPU. In addition, all tracking channels share a tracking loop processing module through time division multiplexing, which effectively saves hardware resources and reduces costs. This paper lays a foundation for the design and development of miniaturized, low-power navigation chips.
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